This invention relates to a semiconductor circuit with a static bootstrap circuit.
Recently, the integration density and operation speed of semiconductor integrated circuits are increasing very much. Particularly, the operation speed on n-channel MOS static random access memories (RAM) has risen as high as that of bipolar RAMs. The increase in the operation speed of this type of RAM, however, increases the power consumption. A static bootstrap circuit has been used to realize a RAM which can operate at a high speed with low power consumption. The power consumption of the bootstrap circuit is low because no steady-state current flows therein. The bootstrap circuit thus can be designed to provide a driving capacity corresponding to the desired driving speed.
The static bootstrap circuit of this type, however, presents problems when it is used under non-synchronous operating conditions. It requires a certain precharge set-up time for its normal bootstrap action. Sometimes a sufficiently long precharge set-up time cannot be provided under non-synchronous operating conditions. In such a case, a sufficiently effective bootstrap action cannot be obtained, leading to reduced operating speed or erroneous operation.
FIG. 1 shows a prior art static bootstrap circuit. This bootstrap circuit includes a depletion type (D-type) MOS transistor TR1 and an enchancement type (E-types) MOS transistor TR2 which have their current paths connected in series between voltage source terminals VD and VS to which a power source voltage VDD and a reference voltage VSS are respectively applied and constitute a delaying inverter DI, and E-type MOS transistors TR3 and TR4 having their current paths connected in series between the voltage source terminals VD and VS. The gate of the MOS transistor TR4 is connected to the output terminal of the inverter DI. A node N1 between the MOS transistors TR3 and TR4 is connected to an output terminal VO. The bootstrap circuit further includes an E-type MOS transistor TR5 connected between the input terminal VI and the gate of the MOS transistor TR3, and a coupling capacitor C1, connected between the node N1 and the gate of the MOS transistor TR3. The voltage source terminal VS may be grounded.
Assume now that an input signal supplied to the input terminal VI begins to rise to a high level or VDD level. In this case, the output signal of the delaying inverter DI goes to a low level or VSS level. The capacitor C1 is thus charged according to the input signal until the MOS transistor TR4 is rendered nonconductive. When the VSS level is reached by the output signal of the delaying inverter DI, the MOS transistor TR4 is rendered nonconductive. As a result, the drain potential on the MOS transistor TR4, i.e., the potential on the node N1, begins to rise sharply toward the VDD level.
The gate potential on the MOS transistor TR3 is thus raised to be equal to or above the sum of the threshold voltage level VTH of the MOS transistor TR3 and VDD level by the bootstrap action of the capacitor C1. The potential on the node N1 thus ultimately reaches the VDD level.
The extent of charging of the coupling capacitor C1 that is necessary for the bootstrap action, depends on the potential difference across the capacitor C1 according to the delay time provided by the delaying inverter DI. This wll now be discussed in detail. To obtain an effective bootstrap action, the capacitor C1 must be sufficiently charged before the MOS transistor TR4 is rendered nonconductive. However, this is liable to fail when the spike noise, or glitch, is introduced into the input signal. Now, it is assumed that the potential on the node N1, i.e., the output signal, is raised to the VDD level as a result of the normal bootstrap action brought about with the rise of the input signal from the VSS level to the VDD level. If the input signal subsequently falls to an intermediate level and then returns to the VDD level in a short period of time, the coupling capacitor C1 is discharged through the MOS transistor TR5. In this case, the output signal falls to the intermediate level later than the fall of the input signal. Therefore, with the rising of the input signal again to the VDD level, a sufficient potential difference for the next bootstrap action is not built up across the capacitor C1. The next bootstrap action is thus insufficient, and the output signal no longer rises to the VDD level, thus causing an erroneous operation of the circuit that is connected to the output terminal VO.